Integrated circuit (IC) designers often use electronic design automation (EDA) software tools to assist in the design process, and to allow simulation of a chip design prior to prototyping or production. IC design using EDA software tools generally involves an iterative process whereby the IC design is gradually perfected. Typically, the IC designer builds up a circuit by inputting information at a computer workstation generally having high quality graphics capability so as to display portions of the circuit design as needed. A top-down design methodology is commonly employed using a hardware description languages (HDL), such as Verilog or VHDL, for example, by which the designer creates an integrated circuit by hierarchically defining functional components of the integrated circuit, and then decomposing each component into smaller and smaller components to eventually produce a layout of the chip.
A number of design choices that generate the layout of an integrated circuit chip may affect the manufacturing yield of the integrated circuit in its monolithic semiconductor substrate. It would be advantageous to provide an EDA software tool that could generate a dynamic visualization of a real-time yield analysis of the layout of an integrated circuit chip to assist designers to visualize the yield impact and perhaps to make design choices that would improve the yield of an integrated circuit.